MIPS

1. Microprocessor without Interlocked Pipeline Stages; a computer architecture.
2. Million Integer-instructions Per Second; a benchmark measure.

See also: Architecture | RISC | SGI

Home Page: http://www.mips.com

Acronym: Microprocessor without Interlocked Pipeline Stages

Wikipedia: http://en.wikipedia.org/wiki/MIPS-architecture

An architecture by MTI. MTI was acquired by SGI in the 90’s. Earlier versions of the MIPS were 32-bit, whereas later versions of the architecture were 64-bit

Computers using the MIPS architecture include:

• SGI Indigo (32-bit). R2000, R3000.
• SGI Indy (64-bit). R4x00, R5000.
• SGI Indigo2 (64-bit). R4400, R10000.
• SGI Octane (64-bit). R10000 and higher.
• SGI O2 (64-bit). R10000 and higher.
• SGI Tezro (64-bit). R10000 and higher.
• Several Cisco routers.
• Nintendo N64 (64-bit). R4300.
• Sony Playstation2 (64-bit). R5000.

Related

• Futuretech: SGI Tech Advice (http://futuretech.mirror.vuurwerk.net/sgi.html).

See also: Benchmarking

Acronym: Million Integer-instructions Per Second :

Aka: MIPS

Acronym: Million Floating-point-instructions Per Second :

Aka: MFLOPS

Related

• Futuretech: MIPS/MFLOPS and CPU Performance (http://futuretech.mirror.vuurwerk.net/perf.html)

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